Electronic design automation (EDA) tools are used for designing, verifying, and implementing electronic systems and component circuits. Within an electronic system, hundreds of integrated circuits, or “chips”, may be interconnected on one or more printed circuit boards (PCBs). Today, an integrated circuit can easily comprise billions of interconnected transistors to enable a set of intended functions. Without EDA tools, it would be impractical, if not impossible, to produce and commercialize an integrated circuit of such complexity. Integrated circuits continue to become more complex (i.e.—increasing number of transistors) with each successive generation of process technology, allowing more transistors to exist on a footprint of the same or smaller size. Increase in complexity generally translates to longer times for designing, verifying, and implementing a chip design. There exists a need for advances in EDA tool technology to keep chip development within a competitive timeline.
The design process for an integrated circuit generally entails describing the circuit's intended behavior at the register transfer level (RTL) using a hardware description language, such as VHDL, or Verilog, and then reducing the RTL design description into a physical layout of transistor gates. However, because the design is implemented to describe the functions of, perhaps, millions or billions of interconnected transistors, errors may be inevitable. Thus, the design needs to be verified to ensure that it behaves exactly the way the designers intended. One possible approach is to reduce the RTL code to a physical layout, fabricate a prototype chip, and then test it in the intended environment. However, the impracticality of such an approach goes without saying in the industry, given the turnaround time, the cost of manufacturing, and the number of design revisions that may be required to perfect the design.
Today, verification engineers utilize a range of EDA tool technologies for logic verification that are far more practical than prototyping. One such technology is software simulation, which refers to running an RTL design through a computer program, a “software simulator”, on a general purpose computer or workstation to simulate the operations of the circuit design. Even though software simulation offers faster turnaround time compared to manufacturing an actual device, simulating a complex circuit design can still be painstakingly slow and can take up to months or more to finish. Indeed, it can take many hours or even several days to simulate just a small number of clock cycles of a typical design if a software simulator is used. This is because a typical workstation relies on a single processor to simulate these operations in a sequential or semi-sequential manner. In contrast, most of the operations on a fabricated chip are performed in parallel.
Hardware emulation is a logic verification technology that typically offers the fastest verification speed because a considerable number of operations may be performed in parallel. Parallel execution is achieved by mapping substantially the entire circuit design onto the emulation resources of a hardware platform. Additionally, with hardware emulation, the hardware platform can run almost independently from a workstation because almost all of the verification environment is placed on the hardware platform. Without having to wait for data input from the workstation, the user's design running in the emulator can operate at substantially full hardware speeds. However, the speed enhancement is not without cost. Because almost the whole design would need to be mapped onto the hardware platform, the complexity of the design is generally limited by the emulation resource capacity of the hardware platform.
Simulation acceleration offers a middle ground in terms of verification speed and emulation capacity between software simulation and hardware emulation by separately executing a software portion and a hardware portion of the design. Code apportionment is performed by a compiler in a workstation at compile time. The hardware portion of the design is mapped onto the emulation resources of the hardware emulation system, which executes the code in a substantially parallel manner, while the software portion of the design runs in the software simulator on the workstation. The workstation is connected to and works in conjunction with the hardware platform to verify the circuit logic through the exchange of simulation data. Because the hardware platform may have to wait for data input from the workstation, verification speed is determined in part by the percentage of the design remaining on the workstation and the communication channel width and latency between the workstation and the hardware platform.